Setting the FTZ and DAZ Flags

In Intel® processors, the flush-to-zero (FTZ) and denormals-are-zero (DAZ) flags in the MXCSR register are used to control floating-point calculations. Intel® Streaming SIMD Extensions (Intel® SSE) and Intel® Advanced Vector Extensions (Intel® AVX) instructions, including scalar and vector instructions, benefit from enabling the FTZ and DAZ flags respectively. Floating-point computations using these Intel® SSE and Intel® AVX instructions are accelerated when the FTZ and DAZ flags are enabled and thus the performance of the application improves.

You can use the [Q]ftz option to flush denormal results to zero when the application is in the gradual underflow mode. This option may improve performance if the denormal values are not critical to your application's behavior. The [Q]ftz option, when applied to the main program, set the FTZ and the DAZ hardware flags. The negative form of the [Q]ftz option leave the flags as they are.

The following table describes how the compiler processes denormal values based on the status of the FTZ and DAZ flags:

• FTZ and DAZ are not supported on all IA-32 architectures. The FTZ flag is supported only on IA-32 architectures that support Intel® SSE instructions.
• On systems based on the IA-32 and Intel® 64 architectures, FTZ only applies to Intel® SSE and Intel® AVX instructions. Hence, if your application happens to generate denormals using x87 instructions, FTZ does not apply.

• DAZ and FTZ flags are not compatible with IEEE Standard 754, so you should only consider enabling them when strict compliance to the IEEE standard is not required.

Options [Q]ftz are performance options. Setting these options does not guarantee that all denormals in a program are flushed to zero. They only cause denormals generated at run-time to be flushed to zero.

On Intel® 64 and IA-32 systems, the compiler, by default, inserts code into the main routine to set the FTZ and DAZ flags. When [Q]ftz option is used on IA-32 systems with the option –msse2 or /arch:sse2, the compiler will insert code to conditionally set FTZ/DAZ flags based on a run-time processor check. Using the negative form of [Q]ftz will prevent the compiler from inserting any code that might set FTZ or DAZ flags.

When the [Q]ftz option is used in combination with an Intel® SSE-enabling option on systems based on the IA-32 architecture (for example, -msse2 or /arch:sse2), the compiler will insert code in the main routine to set FTZ and DAZ. When option [Q]ftz is used without such an option, the compiler will insert code to conditionally set FTZ or DAZ based on a run-time processor check. The negative form of [Q]ftz will prevent the compiler from inserting any code that might set FTZ or DAZ.

The [Q]ftz option only has an effect when the main program is being compiled. It sets the FTZ/DAZ mode for the process. The initial thread and any threads subsequently created by that process will operate in the FTZ/DAZ mode.

On systems based on the IA-32 and Intel® 64 architectures, every optimization option O level, except O0, sets [Q]ftz.

If this option produces undesirable results of the numerical behavior of your program, you can turn the FTZ/DAZ mode off by using the negative form of [Q]ftz in the command line while still benefitting from the O3 optimizations.

You can set the flags manually by calling the following Intel® Fortran intrinsic: